1. Field of the Invention
The present invention relates to an apparatus for reading information such as a video signal or an audio signal recorded in a recording medium such as a disk or a magnetic tape.
2. Description of the Prior Art
In a video disk player, for example, a coarse adjustment of the time base is performed by regulating the rotating speed of the spindle motor for rotating the disk such that the relative speed between the disk and the information detecting point of the pickup as the signal reading means is controlled and a fine adjustment of the time base is performed by supplying a playback signal obtained by the pickup to a variable delay element and regulating the delay time of the playback signal. As the variable delay element for the fine adjustments of the time base, a memory has come to be used more frequently. In the case where the memory is used, a pulse train signal in synchronism with the variation along the time base in the playback signal is generated and the playback signal is written into the memory according to the pulse train signal, and subsequently, the signal is read out from the memory according to a reference pulse signal having a fixed frequency, whereby the playback signal is delayed a period of time corresponding to the variation along the time base and the fine adjustment of the time base is achieved.
Such a prior art video disk player is shown in FIG. 3. Referring to the figure, a disk 1 is driven to rotate by a spindle motor 2. As the disk 1 is rotated, a signal recorded in the disk 1 is read out by a pickup 3. An RF signal output from the pickup 3 is supplied to a demodulation circuit 5 comprising an FM modulator or the like. A video signal is demodulated by the demodulation circuit 5 and the video signal is supplied to an A/D (Analog to Digital) converter 6 and a sync separation circuit 7. In the sync separation circuit 7, a horizontal sync signal included in the video signal is separated and output as a reproduced horizontal sync signal h. The reproduced horizontal sync signal h is supplied to a write clock generating circuit 8, a write address count starting signal generating circuit 9, a phase comparator circuit 10, and a memory controller 11.
The write address count starting signal generating circuit 9 comprises, for example, a differentiation circuit and is adapted to output a write address count starting signal (hereinafter to be called "WST signal") formed of a pulse of negative polarity generated in synchronism with the reproduced horizontal sync signal h.
In the phase comparator circuit 10, the reproduced horizontal sync signal h is compared with a reference horizontal sync signal r, and thereby, a signal corresponding to the phase difference between these signals is generated. The output of the phase comparator circuit 10 is supplied as a spindle error signal to the spindle motor 2 through a servo amplifier 12 so that the rotating speed of the disk 1 is controlled.
In the write clock generating circuit 8, the reproduced horizontal sync signal h is supplied to the phase comparator circuit 15 to be compared with an output of a frequency divider 16, and thereby, a phase difference signal corresponding to the phase difference between these signals is generated. The output of this phase comparator circuit 15 serves as the control input for a VCO (Voltage Controlled Oscillator) 17. The VCO 17 is arranged such that its free-running frequency is virtually equal to four times the frequency f.sub.sc of the color subcarrier. The output of the VCO 17 is supplied to the frequency divider 16 and its frequency is divided therein, for example, by 910. The phase comparator circuit 15, VCO 17, and the frequency divider 16 together form a PLL (Phase Locked Loop), and from the VCO 17, a signal in phase with the reproduced horizontal sync signal h is output. The output of the VCO 17 is supplied to a 1-H line memory 20 as a write clock and also supplied to the A/D converter 6 as a sampling pulse.
In the A/D converter 6, the video signal is subjected to sampling with the use of the output of the VCO 17, whereby digital data corresponding to the obtained sample values is generated. The output data from the A/D converter 6 is supplied to the 1-H line memory 20. To the 1-H line memory 20 are supplied, other than the write clock, the WST signal, a read address count starting signal (hereinafter to be called "RST signal"), and a read clock. The 1-H line memory 20 comprises, for example, a memory having a capacity capable of storing data for one line, a write address counter which is reset by the WST signal and the count value of which is sequentially changed by the write clock, and a read address counter which is reset by the RST signal and the count value of which is sequentially changed by the read clock. The 1-H line memory 20 is adapted, every time the write clock is generated, to write the input data into the memory at the address indicated by the output data of the write address counter, and every time the read clock is generated, to read and output the data written in the memory at the address indicated by the output data of the read address counter. By this 1-H line memory 20, the fine adjustment of the time base is performed.
The data read out of the 1-H line memory 20 is supplied to the field memory 21. The field memory 21 is structured, for example, the same as the line memory 20, except for the storage capacity. The field memory 21 is supplied with various controlling signals from the memory controller 11. The memory controller 11 is supplied with an output of a reference signal generating circuit 23, which is composed of such parts as a quartz oscillator generating a reference signal whose frequency is four times the frequency of the subcarrier, i.e., 4 f.sub.sc. In the memory controller 11, the reference signal of the frequency of 4 f.sub.sc is supplied to a control signal generating circuit 111 and also serves as one of the inputs to a NAND (nonconjunction) gate 112. The control signal generating circuit 111 is arranged to generate various control signals by means of the reference signal of 4 f.sub.sc and supply these signals to the field memory 21, so that input data are written into the field memory 21 sequentially from a predetermined address and the written data are read out sequentially in the order according to an operating mode designated by an operating unit (not shown).
Meanwhile, the reference signal of 4 f.sub.sc passed through the NAND gate 112 is supplied to a frequency divider 113 and its frequency is divided therein by 910. The frequency divider 113 is formed, for example, of a divide-by-910 counter and arranged to output a signal corresponding to the most significant digit of the count value. The output of this frequency divider 113 is supplied to a switching inverter circuit 114. The switching inverter circuit 114 is adapted to alternately deliver the output of the frequency divider 113 and the signal obtained by inverting the output of the frequency divider 113 every time, for example, a phase shift command is issued. More particularly, at every issuance of the phase shift command, the output of the switching inverter circuit 114 is inverted so that its phase is shifted by .pi.. The switching inverter circuit 114 is constructed, for example, as shown in FIG. 3B of a switch 201 alternatively relaying the input signal to and the output signal from an inverted 200 and a flip-flop 202 triggered by the phase shift command from the phase shift command generating circuit 115 so as to set on or off the switch 201. The output of the switching inverter circuit 114 is supplied to various parts as a spindle reference signal. Thus, as long as a signal of a logical "1" is supplied to the other input terminal of the NAND gate 112, the reference signal is supplied to the frequency divider 113, so that the spindle reference signal of a predetermined frequency is generated.
On the other hand, a monostable multivibrator 116 is triggered by the leading edge of a jump command pulse a, which is generated in a special playback mode such as scan, still picture playback, and double-speed playback, and generates a single pulse with a predetermined width of negative polarity. The pulse width of the single pulse of negative polarity is set to be longer than the period required for the information detecting point of the pickup 3 to make one track jump operation. This single pulse of negative polarity is supplied to the D input terminal of a D flip-flop 117. To the clock input terminal CK of the D flip-flop 117 is supplied the reproduced horizontal sync signal h through an inverter 118. The Q output of the D flip-flop 117 is supplied to the other input terminal of the NAND gate 112.
Thus, when the reproduced horizontal sync signal h is generated for the first time after the jump command pulse a has been generated, the D flip-flop 117 is reset and the counting operation of the frequency divider 113 is stopped. The D flip-flop 117 is set by the reproduced horizontal sync signal h incoming for the first time after the single pulse as the output of the monostable multivibrator 116 has decayed, and thereby, the counting operation of the frequency divider 113 is started again. Since the ouput of the frequency divider 113 passed through the switching inverter circuit 114 becomes the spindle reference signal, the phase of the spindle reference signal relative to the reproduced horizontal sync signal h immediately after the jump operation changes and comes into agreement with the phase of the same relative to the reproduced horizontal sync signal h immediately before the jump operation. Since the RST signal is generated in synchronism with the spindle reference signal as described later and the WST signal is generated in synchronism with the reproduced horizontal sync signal h, the time difference between the RST signal and WST signal immediately after the jump comes into agreement with the time difference between the RST signal and WST signal immediately before the jump.
The spindle reference signal, together with the reproduced horizontal sync signal h, is supplied to the shift command generating circuit 115. The shift command generating circuit 115 is adapted to detect, by means of the spindle reference signal and the reproduced horizontal sync signal h, that either one of the WST signal and the RST signal, after it was once generated, has been generated again before the other one is generated, to thereby generate the phase shift command signal.
The spindle reference signal generated in the memory controller 11 is supplied to an RST signal generating circuit 24 and a reference sync signal generating circuit 25. The RST signal generating circuit 24 is formed, for example, of a differentiation circuit and adapted to output the RST signal in synchronism with the trailing edge of the spindle reference signal.
The phase shift command signal output from the memory controller 11 is supplied to a phase shift controlling circuit 26. The phase shift controlling circuit 26 is arranged to output an acquisition operation command signal, for example, extending over the time equal to the period of the spindle reference signal from when the phase shift command signal has been generated. The output of the phase shift controlling circuit 26 is supplied to the reference sync signal generating circuit 25. The reference sync signal generating circuit 25 is adapted to take in the spindle reference signal while the acquisition operation command signal is supplied and output it as the reference horizontal sync signal r. As the reference sync signal generating circuit 25, such a circuit can be used which is made up, for example, of a divide-by-910 counter which counts up upon receipt of the 4 f.sub.sc reference signal and outputs a signal corresponding to the most significant bit of the count value data as the reference horizontal sync signal r and others and adapted such that the count value is reset in response to the trailing edge of the spindle reference signal, while the acquisition operation command signal is output from the phase shift controlling circuit 26.
On the other hand, data read out from the field memory 21 is supplied to the D/A converter 27 and converted into an analog signal. From this D/A converter is output a playback video signal.
With the above described construction, during a normal playing operation, the allowance for jitter in the playback video signal becomes maximum when there is a time difference of 1H/2 (.apprxeq.32 .mu.s) on an average between the WST signal obtained from the reproduced horizontal sync signal h and the RST signal output from the RST signal generating circuit 24. Because of this, it is arranged such that, after the spindle reference signal in synchronism with the RST signal is taken in as the reference horizontal sync signal r, the spindle error signal corresponding to the phase difference between the reference horizontal sync signal r and the reproduced horizontal sync signal h is generated in the phase comparator circuit 10, whereby the rotating speed of the spindle motor 2 is controlled so that the time difference between the WST signal and the RST signal may become 1H/2 on an average.
When a jump operation is performed in the described apparatus during its reading operation of the recorded information with a CLV (constant linear velocity) disk, the reproduced horizontal sync signal h becomes discontinuous and its period is disturbed so that a phase difference is produced between the spindle reference signal and the reference horizontal sync signal r. Then, the time deference between the WST signal and the RST signal is disturbed, so that the timing of the generation of the WST signal is advanced or delayed with reference to the RST signal. However, it is arranged such that, if either one of the WST signal and the RST signal was once generated and then the same signal has been generated again before the other one is generated, the spindle reference signal output from the memory controller 11 is inverted and, at the same time, the phase shift command signal is output, whereby the inverted spindle reference signal is taken in as the reference horizontal sync signal r and the time difference between the WST signal and the RST signal becomes equal to 1H/2 again.
However, the phase shift command signal is output in the above described prior art apparatus only when, after either one of the WST signal and the RST signal was generated, the same signal has been generated again before the other one is generated, and therefore, there has been such a problem, for example, that the information at an address once read is read again before it is altered so that the same image is played back during two horizontal periods.